Chip-size package with an integrated passive component

ABSTRACT

A passive component is integrated into a product having a rewiring location.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based on and hereby claims priority to GermanApplication No. 102 03 397.8 filed on Jan. 29, 2002, the contents ofwhich are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. The Field of the Invention

The invention relates to a product and a method for fabricating aproduct.

2. Description of the Related Art

The trend in packaging and interconnection technology is resulting inever smaller IC package designs. With the chip-size packages, the ICpackage is scarcely larger than the silicon area itself. Conversion ofthe bare chips to chip-size packages takes place at wafer level in thecase of the most inexpensive method, wafer level packaging. With anadditional insulating layer and a patterned metallization layer, theclosely adjacent chip pads at the chip edges are planarly distributed onthe chips in a grid.

The chip-size package is mounted on a wiring substrate andinterconnected with passive components.

U.S. Pat. No. 6,025,647 discloses a product with a rewiring layer havingan additional passive component.

SUMMARY OF THE INVENTION

An object of the invention is to specify a product and a method forfabricating a product wherein the cost-intensive and space-consumingsubsequent interconnection of the product with passive components on awiring substrate can be dispensed with.

The product accordingly has contact pads. These product contact pads areused for contacting circuits contained in the product. On the product,preferably on at least one side of the product, there is disposed arewiring layer.

The rewiring layer preferably includes at least one insulating layer anda patterned metallization layer. The insulating layer is built up on theproduct. Depending on the thickness of the insulating layer, themetallization layer—as a conductor level additively newly created on theinsulating layer—lies on average 5 to 10 μm above the product (chipcircuit).

A clear advantage is that, using this approach, the thickness of one ormore, or all of the insulating layers can in each case be kept to lessthan 20 μm, more specifically to less than 10 μm. Typical layerthicknesses are even in the 5 μm range, thereby enabling a multilayerwiring substrate to be implemented in the form of a rewiring layerhaving a thickness in the 15 μm range or below.

In addition, the close proximity of metallization level and product andthe building-up of the metallization layer on the product obviate theneed for additional interconnection systems. By extending so far in, themetallization level is therefore connected to the product or productcontact pads directly, i.e. without gluing, soldering or (wire) bonding.

The patterned metallization layer basically provides rewiringconnections for contacting the product contact pads with rewiringcontact pads. From these rewiring contact pads the product can befurther contacted when it is mounted on a wiring substrate, e.g. aprinted circuit board.

The rewiring layer further has, in addition to a rewiring connection, atleast one passive component between at least one product contact pad andat least one rewiring contact pad. Essentially each rewiring connection,which can be implemented e.g. in the form of a rewiring conductor track,itself constitutes a passive component having a resistance, acapacitance and an inductance. The additional passive component isinserted over and above the rewiring connection in order to produce arequired resistance, capacitance and/or inductance value, therebyobviating the need for subsequent interconnection with external passivecomponents and for the components themselves, or else the number ofcomponents can be reduced.

The passive component contains a dielectric and/or a resistive materialor is implemented thereby. Possible dielectrics are titanium oxide TiO₂and/or tantalum oxide Ta₂O₃ which can be applied e.g. by a sputteringprocess and photolithographically patterned. Materials having anelevated resistance value compared to the specific resistance value ofthe rewiring material are preferably to be used as the resistivematerial.

The fabrication of the passive component can be very favorablyintegrated in the manufacturing process if the component is disposedbetween the product contact pad and/or rewiring contact pad on the onehand and the rewiring connection on the other, the most cost-effectivesolution being to dispose it between the product contact pad and therewiring connection.

The passive component is preferably disposed within the rewiring layerto produce a particularly compact and easily mountable design.

The passive component can be a resistor, a capacitor and/or an inductor.

The product is more specifically a semiconductor device and/or a surfaceor bulk wave device in the form of a chip. The product and rewiringlayer then together form a chip-size package.

In order to set the value of the passive component to a required value,the product contact pad and/or the rewiring contact pad can be at leastpartially covered by another insulating layer which only leaves apredefined size of contact pad opening.

A further or additional way of setting the value of the passivecomponent consists in appropriately selecting the dielectric constantand/or the thickness of the dielectric or the thickness and/or thespecific resistance value of the resistive material.

In addition to disposing it between contact pad and rewiring connection,the dielectric and/or the resistive material for implementing thepassive component can also be disposed in a break in the rewiringconnection. Here too options exist for setting a required value of thepassive component, e.g. by the length of the break and/or by selectingthe dielectric having a required dielectric constant and/or theresistive material having a required specific resistance.

Particularly for use in a chip-size package, the rewiring layer has aheight of 3 to 30 μm.

A method for fabricating a product with a rewiring layer having apassive component as well as embodiments of the method will emergeaccordingly from the described preferred embodiments of the product withthe rewiring layer.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects and advantages of the present invention willbecome more apparent and more readily appreciated from the followingdescription of an exemplary embodiment with reference to theaccompanying drawings of which:

FIG. 1 is a cross sectional view of a product with a rewiring layer.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Reference will now be made in detail to the preferred embodiments of thepresent invention, examples of which are illustrated in the accompanyingdrawings, wherein like reference numerals refer to like elementsthroughout.

FIG. 1 shows a product 1 in the form of a silicon chip and having aproduct contact pad 2 in the form of an aluminum pad. In the area of theproduct 1 not covered by the product contact pad 2, it has on itssurface a first passivation layer 3 of silicon nitrite (Si₃N₄) on whichthere is disposed a second passivation layer 4 of polyimide as aninsulating layer. A layered structure of this kind is generally alreadyproduced in front-end operations.

The packaging process begins with the application of a passivation layer5 in the form of another polyimide insulating layer on the wafer, thesize of the further insulating layer 5 being set via the product contactpad 2 in order to control the value of the passive component to beincorporated in the rewiring layer, i.e. to determine the capacitance ofan integrated capacitor, for example.

A suitable dielectric 6, e.g. titanium oxide or tantalum oxide, is thenapplied by sputtering or other suitable method and photolithographicallypatterned in such as way that is covers the product contact pad openingin the further insulating layer 5.

An adhesive layer 7 of e.g. titanium and copper is then applied in theregion in which a rewiring connection will subsequently be created.

This is followed by another photolithographic patterning step forcreating the rewiring connection 8 which is produced by electroplatinge.g. with CuNiAu. Applied photoresist is then delayered and thesuperfluous titanium-copper areas are etched.

This is followed by the application of a fourth passivation layer 9which again may be polyimide and can also be used as solder resist.

An opening is produced in the fourth passivation layer 9, preferablyphotolithographically, via the rewiring connection 8. A rewiring contactpad 10 in the form of a solder ball for contacting on a wiring substratesuch as a printed circuit board is then produced by solder paste stencilprinting and a reflow process.

In the example illustrated, a passive component essentially having acapacitance value and therefore functioning as a capacitor isimplemented by the dielectric 6 between the product contact pad 2 on theone hand and the rewiring connection 8 on the other. The capacitance canbe set by the size of the opening of the further insulating layer 5above the product contact pad 2 and by the thickness and dielectricconstant of the dielectric 6.

A passive component essentially having a resistance value and thereforefunctioning as a resistor can be implemented, for example, by a break inthe rewiring connection. The resistance value can be varied by thelength and width of the break in the rewiring connection as well as thethickness and specific resistance of the resistive material selected.

All in all, a passive component can be inexpensively incorporated in therewiring layer by a single additional patterned layer.

The invention has been described in detail with particular reference topreferred embodiments thereof and examples, but it will be understoodthat variations and modifications can be effected within the spirit andscope of the invention.

1-10. (canceled)
 11. A rewiring layer in a device having device contactpads, comprising: rewiring contact pads; rewiring connections betweenthe device contact pads and said rewiring contact pads; and at least oneelectrically passive component, formed of at least one of a dielectricand a resistive material, each separating at least one of said rewiringconnections from at least one of the device and rewiring contact pads.12. A rewiring layer according to claim 11, wherein said electricallypassive component is one of a resistor, a capacitor and an inductor. 13.A rewiring layer according to claim 12, wherein the device is one of asemiconductor device, a surface wave device and a bulk wave device. 14.A rewiring layer according to claim 13, wherein said electricallypassive component is formed of at least one of titanium oxide andtantalum oxide.
 15. A rewiring layer according to claim 14, furthercomprising an insulating layer at least partially covering at least oneof the device and rewiring contact pads and setting a value of saidelectrically passive component.
 16. A rewiring layer according to claim15, wherein the rewiring layer has a height of 3 μm to 30 μm.